1. Field of the Invention
The present invention relates in general to memory arrays, and more particularly to techniques to increase the density of memory elements in a flash EPROM array.
2. Description of the Related Art
To reduce the size of memory cells in a flash EPROM array, and thus increase density, the structure of individual memory cells as well as the procedure for erasing the individual cells has been considered. To facilitate understanding how array density is increased, conventional flash EPROM cells and conventional procedures for erasing the cells are first described.
FIG. 1 shows a cross-sectional view of a conventional flash EPROM cell transistor 10 as fabricated in a flash EPROM array. The layers of the cell 10 are fabricated utilizing a wafer having a first conductivity type dopant, typically p-type.
A source region 16 and drain region 18 adjacent to the surface of the substrate 12 are provided by doping the substrate 12 with an n-type dopant to form regions of a second conductivity type, typically n-type, as shown. A short channel region 20 is defined by the area of the substrate adjacent the surface between the source 16 and drain 18 regions which remains p-type.
Layers of dielectric material 22 are deposited above the substrate 12 to isolate the substrate 12 from layers of the flash EPROM cell 10 which are to be deposited above the substrate 12. The dielectric material 22 is typically formed from silicon dioxide, also referred to as oxide. Dielectric material 22' is also shown which is utilized to form flash EPROM cells other than cell 10 which are additionally included in the flash EPROM array.
Provided above the channel 20 and a portion of the source 16 and drain 18 is a floating gate 24. The floating gate 24 is typically formed from a semi-conductive poly-silicon material which is isolated from the substrate by a layer of the dielectric material 22.
Provided above the floating gate 24 is a control gate 28 which is also typically formed from a poly-silicon material. The control gate 28 is isolated from the floating gate by a layer of the dielectric material 22.
A layer of conductive material is deposited to form a source line 32, control gate line 34 and a drain line 36 provided above the source 16, control gate 28 and drain 18 of the flash EPROM cell 10 respectively. The conductive lines 32, 34 and 36 are typically formed from metal and enable external electrical connections to be made to the source 16, control gate 28 and drain 18 respectively.
To program the core cell 10 a typical gate voltage of 9-12 V is applied to the control gate line 34, a typical drain voltage of 5-6 V is applied to the drain line 36 and the source line 32 is grounded. The voltages applied during programming enable electrons in the channel region 20 to overcome the energy barrier existing between the substrate 12 and the oxide 22 enabling the electrons to be driven onto the floating gate 24. The electrons stored on the floating gate 24 increase the threshold voltage of the cell, or the gate-to-source voltage potential difference required to turn the cell on. The floating gate 24 thereby stores charge representing a data bit.
In a conventional erase procedure, termed source erase, a potential difference is created by applying a gate voltage of approximately -10 V to the control gate line 34 and a source voltage of approximately +5 V to the source line 32 while floating the drain line 36. The voltage difference between the control gate 28 and source 16 enables electrons to be driven from the floating gate 24 to the source 16.
To reduce the size of a cell, and thus increase array density, it is desirable to reduce the channel length 20. But there is a limit to how much the channel length can be reduced due to band-to-band tunneling leakage current at the source when source erase is utilized. With the leakage current, power supplies in the array will not provide sufficient current to erase the cells. To prevent the leakage current, a double-diffused implant (DDI) is typically included at the source to reduce band-to-band tunneling and eliminate the leakage current from the source.
FIG. 2 shows a cross-section of a flash EPROM cell with a double-diffused source region 200. To create the double-diffused source region 200 a lightly doped n-type implant 202 is formed along the outer periphery of a heavily doped n.sup.+ -type implant region 204. The "+" symbol is utilized to indicate heavily doped as opposed to lightly doped regions.
With the n-type region 202 along the outer periphery of an n+-type region 204, the channel 20 can be slightly reduced from a typical n-type source region without a double-diffused source implant. However, with the n-type region 202 along the outer periphery of the source 204, the minimum size of the channel 20 is ultimately also limited. To increase array density, it is, therefore, desirable to reduce the channel size without including a double-diffused source implant.
A proposed alternative to the conventional source erase procedure is an erase procedure termed channel erase. Channel erase is accomplished by creating tunneling from the floating gate of a cell to its substrate rather than from the floating gate to the source as in source erase. An advantage of channel erase is that no band-to-band tunneling leakage current is generated during erase.
FIG. 3 shows an array of flash EPROM memory cells configured to employ channel erase. In order to control charge flow from the channels to provide channel erase, the memory cells are provided in a p-type well 300 which is isolated from the remainder of the substrate 12. The p-well 300 is isolated from the remainder of the substrate 12 by an n-well 302. To provide a connection to the substrate to enable channel erase, a p.sup.+ -type tap region 304 is provided in the p-well 300. A conductive channel line, C, is further deposited above the tap region to enable external connection to the tap region 304.
To employ channel erase, a potential difference is created by applying a gate voltage of approximately -8 V to the control gate line of a given memory cell while providing a channel voltage of approximately 8 V to the channel line. The voltage difference between the control gate line and channel line enables electrons to be driven from the floating gate of the given memory cell through its channel and through the p-well 300 and tap 304 into the channel line.
Usually the p-well 300 is lightly doped, and therefore has a high resistance. Because of the different lengths from the channels of memory cells to the tap region 304, different resistances illustrated by resistors R.sub.1-3 occur in the p-well 300. In other words, the p-well creates a series resistance between channels of the memory cells.
During both programming and erase operations, a large amount of substrate current can be generated. With a high p-well resistance the large substrate current can de-bias the p-well 300 further increasing the values of resistances R.sub.1-3 and preventing proper programming or erase from occurring.
FIG. 4 shows the array of flash EPROM memory cells of FIG. 3 configured to prevent the large series resistance during channel erase. The design of FIG. 4 prevents the high series resistance by including additional p.sup.+ -type tap regions, such as taps 401 and 402, spaced periodically in the memory array.
Although the design of FIG. 4 overcomes the high series resistance, the taps, such as 401 and 402, reduce the overall area available for cell layout. To increase array density, it is therefore not desirable to include taps 401-403.